The present invention relates to a semiconductor memory device, and more particularly, to a method for testing for interference between adjacent cells that reduces time and prevents noise.
An adjacent cell interference test is conducted on semiconductor devices, especially DRAMs. During the adjacent cell interference test, a certain word line remains selected for a predetermined time, and a sense amplifier amplifies the cell information read from a bit line. Then, interference is detected from the cell information stored in a memory cell connected to the adjacent word line.
Due to the increase in the memory capacity of semiconductor memory devices, the number of word lines has increased. This has lengthened the time required to conduct the adjacent cell interference test. To save testing costs, it is required that the testing time be reduced. Therefore, a multiple word line selection test is conducted to simultaneously activate a plurality of word lines. In this test, it is required that the number of simultaneously selected word lines be increased and abnormal functioning caused by noise be prevented.
FIG. 1 is a circuit diagram of a memory cell array and its peripheral circuits in a semiconductor memory device (DRAM) 50. The memory cell array has four memory cell blocks BL0, BL1, BL2, BL3. Sense amp groups 1 and row decoders 2 are adjacent to the blocks BL0–BL3. Each sense amp group 1 includes a plurality of sense amps 8.
The peripheral circuits include sense amp drive circuits 3, block control circuits 4, a timing signal generation circuit 5, a block address buffer 6, and an address buffer 7. The sense amp drive circuits 3 are each associated with one of the sense amp groups 1. The block control circuits 4 are each associated with one of the blocks 0–3.
The sense amp drive circuits 3 and the block control circuits 4 receive a timing signal from the timing signal generation circuit 5. The block control circuits 4 receive a block address signal Bad from an external device via the block address buffer 6.
The block control circuits 4 generate a word line set signal WLst, which activates word lines, and a word line reset signal WLrs, which inactivates word lines. Further, the block control circuits 4 provide the associated row decoders 2 with the set signal WLst and the reset signal WLrs.
Based on the timing signal and the block address signal Bad, the block control circuits 4 generate a block selection signal Bs1 and provide the associated sense amp drive circuits 3 with the block selection signal Bs1. Based on the block selection signal Bs1, the sense amp drive circuits 3 provide the associated sense amp groups 1 with sense amp drive signals PSA, NSA.
The row decoders 2 receive a word line address signal WLad from an external device via the address buffer 7. The row decoders 2 select word lines based on the word line address signal WLad and the word line set signal WLst and terminates the selection of word lines based on the word line reset signal WLrs.
FIG. 2 is a diagram showing the memory cell array and its peripheral circuits in a single memory cell block. The memory cell block includes, for example, 128 word lines WL0–WL127. A plurality of sense amps 8 are connected to bit lines BL, which intersect each of the word lines WL0–WL127.
In response to the block selection signal Bs1 received from the block control circuit 4, the sense amp drive circuit 3 provides each sense amp 8 with the sense amp drive signals PSA, NSA.
The row decoders 2 select word lines in response to the word line address signal WLad and the word line set signal WLst, which are provided in response to the word lines WL0–WL127. Further, in response to the word line reset signal WLrs, the row decoders 2 terminates the selection of word lines.
The block control circuits 4, the sense amp drive circuits 3, and the row decoders 2 will now be discussed with reference to FIG. 3.
Each block control circuit 4 includes a block selection circuit 9, a word line set signal generation circuit 10, and a word line reset signal generation circuit 11. The block selection circuit 9 receives the block address signal Bad at a high level and a block set timing signal Bstt at a high level. The timing signal Bstt is received from the timing signal generation circuit 5. The block selection circuit 9 has a latch circuit 12a and two inverter circuits 13a to generate the block selection signal Bs1 at a high level in response to the block address signal Bad and the high timing signal Bstt.
When the block selection circuit 9 receives a high block reset timing signal Brst from the timing signal generation circuit 5, the latch circuit 12a and the inverter circuits 13a generate the block selection signal Bs1 at a low level.
The word line set signal generation circuit 10 includes a NAND circuit 14a and an inverter circuit 13b. The NAND circuit 14a has a first input terminal, which receives the block selection signal Bs1, and a second input terminal, which receives a word line set timing signal WLstt from the timing signal generation circuit 5. The inverter circuit 13b receives the output signal of the NAND circuit 14a and generates the word line set signal WLst.
When the word line set signal generation circuit 10 receives the block selection signal Bs1 at a high level and the word line set timing signal WLstt at a high level, the word line set signal generation circuit 10 generates the word line set signal WLst at a high level.
The word line reset signal generation circuit 11 includes a NAND circuit 14b and inverter circuits 13c, 13d. The NAND circuit 14b has a first input terminal, which receives the block selection signal Bs1, and a second input terminal, which receives a word line reset timing signal WLrst from the timing signal generation circuit 5 via the inverter circuit 13c. The two inverter circuits 13d receive the output signal of the NAND circuit and generate the word line reset signal WLrs.
When the word line reset signal generation circuit 11 receives the block selection signal Bs1 at a high level and the word line reset timing signal WLrst at a low level, the word line reset signal generation circuit 11 generates the word line reset signal WLrs at a low level. The word line reset signal generation circuit 11 generates the word line reset signal WLrs at a high level when such signals are not received.
The sense amp drive circuit 3 includes a NAND circuit 14c, inverter circuits 13e, 13f, and transistors Tr1–Tr4. The NAND circuit 14c has a first input terminal, which receives the block selection signal Bs1, and a second input terminal, which receives a sense amp timing signal SAt from the timing signal generation circuit 5.
The output signal of the NAND circuit 14c is provided to the gates of the p-channel MOS transistor Tr1 and the n-channel MOS transistors Tr2, Tr3 via the two inverter circuits 13e. The output signal of the inverter circuit 13e is provided to the gate of the n-channel MOS transistor Tr4 via the inverter circuit 13f. 
The transistors Tr1–Tr4 are connected in series between power supplies Vcc and Vss. A sense amp drive signal PSA is generated at a node of the transistors Tr1, Tr2. A sense amp drive signal NSA is generated at a node of the transistors Tr3, Tr4. A node of the transistors Tr2, Tr3 is supplied with precharge voltage Vp.
When the NAND circuit 14C receives the block selection signal Bs1 at a high level and the sense amp timing signal SAt at a high level, the transistors Tr1, Tr4 are activated and the transistors Tr2, Tr3 are inactivated. This generates the sense amp drive signal PSA at a voltage that is substantially the same as that of the power supply Vcc and the sense amp drive signal NSA at a voltage that is substantially the same as that of the power supply voltage Vss.
When either the block selection signal Bs1 or the sense amp timing signal SAt goes low, the transistors Tr1, Tr4 are inactivated and the transistors Tr2, Tr3 are activated. This generates the sense amp drive signals PSA, NSA at a voltage that is the same as the precharge voltage Vp.
When the row decoder 2 receives the world line set signal WLst at a high level and the word line address signal WLad at a high level, the row decoder 2 generates a word line selection signal WL at a high level by means of a latch circuit 12b and two inverter circuits 13g. When the row decoder 2 receives the word line reset signal WLrs at a high level, the output terminal of the latch circuit 12b goes low. In this state, the row decoder 2 generates the word line selection signal WL at a low level by means of the inverter circuit 13g. 
The operation of the block control circuit 4, the row decoder 2, and the sense amp drive circuit 3 will now be discussed with reference to FIG. 4.
The block set timing signal Bstt is a pulse signal. The block reset timing signal Brst goes low before the first pulse, of the block set timing signal Bstt. Further, the block reset timing signal Brst goes high after the word line reset timing signal WLrst goes high.
If the block set timing signal Bstt goes high when the block selection circuit 9 is provided with the block address signal Bad, which selects one of the blocks BL0–BL3, the block selection signal Bs1 goes high.
When the block selection signal Bs1 goes high and the word line set signal generation circuit 10 is provided with a word line set timing signal WLstt, which is a pulse signal, the word line set signal generation circuit 10 generates the word line set signal WLst, which is a pulse signal.
In the word line reset signal generation circuit 11, the word line reset timing signal WLrst goes low before the first pulse of the word line set timing signal WLstt and goes high when the word line selection signal WL goes low, The word line reset signal WLrs goes high when the word line reset timing signal WLrst goes high.
The sense amp timing signal SAt goes high after a predetermined time from when the word line set timing signal WLstt goes high and goes low after a predetermined time from when the word line reset timing signal WLrst goes high.
If the sense amp timing signal SAt goes high when the sense amp drive circuit 3 receives the block selection signal Bs1 at a high level, the sense amp drive circuit 3 outputs the sense amp drive signals PSA, NSA. When the sense amp timing signal SAt goes low, the sense amp drive signals PSA, NSA shift to the precharge voltage Vp and inactivate the associated sense amps 8.
The word line address signal WLad goes high every predetermined time. Each time the word line address signal WLad goes high, a pulse of the word line set signal WLst is provided to the row decoder 2.
The voltage of the word line WL corresponding to the word line address signal WLad goes high when the word line set signal WLst goes high. The voltage of each word line WL goes low when the word line reset signal WLrs goes high.
A first example of the adjacent cell interference test conducted on the prior art semiconductor memory device 50 will now be discussed with reference to FIG. 5.
Subsequent to a test mode entry command, the semiconductor memory device 50 is provided with an active command every predetermined time. In synchronism with each active command, the semiconductor memory device 50 is provided with the word line address signal WLad and the block address signal Bad. Based on the operation of the block control circuit 4, the row decoder 2 selects a word line and the sense amp drive circuit 3 activates a sense amp.
Referring to FIG. 5, for example, block BL0 is selected. Further, each active command selects every eight word lines in a manner such as WL0, WL8, and WL16.
The sense amp drive signals PSA, NSA simultaneously provide all of the sense amps 8 in block BL0 after a predetermined time from when word line WL0 is selected. A memory cell connected to the selected word line provides the bit lines with cell information. Each sense amp 8 amplifies the cell information. This state is maintained for a predetermined time.
Then, after a predetermined time elapses, the word line reset aiming signal WLrst, which is based on the precharge command, is provided to the word line reset signal generation circuit 11 and the selected word lines are simultaneously inactivated. The sense amp timing signal SAt inactivates the sense amps 8. In this state, it is checked whether the activation of the word line caused interference between adjacent cells.
Subsequently, in response to the active command, every eight word lines in block SL0 are selected sequentially in a manner such as WL1, WL9, and WL17. In this state, the sense amp drive signals PSA, NSA are simultaneously provided to all of the sense amps 8 in block BL0 after a predetermined time from when the sense amp drive signals PSA, NSA select word line WL1. The sense amps 8 amplify the cell information provided to the bit line and maintain the amplified state for a predetermined time.
Such operation is repeated until all of the word lines in the block BL0 are selected. Further, the same operation is performed in blocks BL1–BL3.
In this case, multiple word lines are simultaneously selected. Thus, in comparison to when the word lines are activated one by one, the test time is reduced. However, although multiple word lines are simultaneously selected in each of blocks BL0–BL3 in the first example, word lines of multiple blocks cannot be simultaneously selected. As a result, test time cannot be sufficiently reduced.
A second prior art example of the adjacent cell interference test will now be discussed with reference to FIG. 6. In the second prior art example, multiple word lines of multiple blocks, for example, blocks BL0 and BL2, are simultaneously selected. Further, multiple word lines of blocks BL1 and BL3 are simultaneously selected. This reduces test time.
In synchronism with the first two active commands following the test mode entry command, the semiconductor memory device 50 is sequentially provided with the block address signal Bad, which selects the blocks BL0. BL2. Blocks BL0, BL2 are selected based on the block address signal Bad. The word line address signal WLad first selects the word line WL0 continuously for two times and then selects every eight word lines in a manner such as WL8, WL16.
The first two active commands sequentially activate word lines WL0 of blocks BL0, BL2. Subsequently, every eight word lines of blocks BL0, BL2 are sequentially and simultaneously selected. The sense amps 8 of blocks BL0, BL2 are activated after a predetermined time from the selection of word line WL0 in block BL2. The activated state is maintained for a predetermined time.
Then, the selected word lines are simultaneously inactivated in response to the precharge command. The sense amps 8 are also inactivated.
The operation performed by the block control circuit 4, the sense amp drive circuit 3, and the row decoder 2 to conduct the adjacent cell interference test of FIG. 6 will now be discussed with reference to FIG. 7.
In the operation of FIG. 7, the block address signal Bad is sequentially provided to sequentially select blocks BL0, BL2, and the block set timing signal Bstt sequentially selects blocks BL0, BL2.
The word line address signal WLad, which selects word line WL0, is provided for two cycles so that word line WL0 is selected in blocks BL0, BL2. The other operations, which the blocks undergo, are performed in the same manner as the first example.
In the second example, multiple word lines of multiple blocks are simultaneously selected. This further shortens the test time from that of the first example. However, when the word lines are selected, many sense amps are simultaneously activated in multiple blocks. Further, when selected word lines become no longer selected, many sense amps are simultaneously inactivated. The activation and inactivation of the sense amps produces a switching noise in the power supply. The switching noise may cause the semiconductor memory device 50 to function erroneously.
The timing for activating sense amps is the same in the blocks. However, the timing for starting the selection of word lines differs between the blocks. This results in a shortcoming in that the margin for amplifying the sense amps is not constant. In other words, time t1, which is required to activate the sense amps 8 after word line WL0 is selected in block BL0, is longer than time t2, which is required to activate the sense amps 8 after word line WL0 is selected in block BL2.
Thus, the margin for amplifying the cell information when word line WL0 is activated in block BL0 decreases. This problem occurs because multiple blocks are operated at the same timing.
In other words, in the second prior art example, the block address signal Bad and the word line address signal WLad are provided to simultaneously select multiple word lines in multiple blocks. Further, the sense amps are activated and inactivated at the same timing.